VHDL implementation of DES algorithm / Emmanvel Kajan Mering

Emmanvel, Kajan Mering (2004) VHDL implementation of DES algorithm / Emmanvel Kajan Mering. Undergraduates thesis, University of Malaya.

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    This project is about the development of DES in hardware. DES, and it's variants (tripleDES) are the main encryption methods used in industry today. The DES designed should be able to process a 64-bit data block and it's 64-bit key and produces a 64-bit encrypted output. It also acts as decryptor, which is done by entering the 64-bit encrypted data together with the sub-key (operate in decrypt mode, where key is entered in reverse order). In order for our DES to work, modules are designed. These modules are controller, RAM, the DES core (initdata) and sub-key generator. All these submodules are developed, and then integrated as a complete DES cryptosystem. This DES system will be developed using VHSIC Hardware Description Language (VHDL). This is a complete report, from the designing phase up to the system testing at the end.

    Item Type: Thesis ( Undergraduates)
    Additional Information: Academic Exercise (Bachelor’s Degree) – Faculty of Computer Science & Information Technology, University of Malaya, 2004.
    Uncontrolled Keywords: Algorithm; VHSIC Hardware Description Language (VHDL)
    Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
    T Technology > T Technology (General)
    Divisions: Faculty of Computer Science & Information Technology
    Depositing User: Mr Mahadie Ab Latif
    Date Deposited: 24 Feb 2020 02:42
    Last Modified: 24 Feb 2020 02:42
    URI: http://studentsrepo.um.edu.my/id/eprint/10757

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