VHDL description for IP Engine / Zeliall Bathich

Zeliall, Bathich (2000) VHDL description for IP Engine / Zeliall Bathich. Undergraduates thesis, University of Malaya.

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    Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable and reusable components. Therefore it obtains the integration of advanced tools for the development of the IP Engine into the design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of this Engine is embedded in an approach to develop flexible and configurable protocol engines that can be optimized for specific application. By implementing the IP Engine in hardware it will help reducing communication bottlenecks replacing expensive software solutions. which are based on 32 bit processor cores. With its small footprint design it will improve low power-consumption. Highly cost-effective solution to Perform all protocol functions of TCP/IP and UDP/IP connections for sustained bit rates of up to 100 Mbps independent of packet payload sizes and other connection parameters.

    Item Type: Thesis ( Undergraduates)
    Additional Information: Academic Exercise (Bachelor’s Degree) – Faculty of Computer Science & Information Technology, University of Malaya, 2000/2001.
    Uncontrolled Keywords: VHDL; IP Engine; Network; Communication bottlenecks; Hardware
    Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
    Divisions: Faculty of Computer Science & Information Technology
    Depositing User: Mr Mohd Safri Tahir
    Date Deposited: 11 Apr 2019 08:28
    Last Modified: 17 Aug 2020 07:20
    URI: http://studentsrepo.um.edu.my/id/eprint/9932

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