A pipelined multiplier accumulator focusing on pipeline architecture / Laili Erni Hitam

Laili Erni, Hitam (2003) A pipelined multiplier accumulator focusing on pipeline architecture / Laili Erni Hitam. Undergraduates thesis, University of Malaya.

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    The Pipelined Multiplier Accumulator has brought many approaches and changes to the conventional MAC. The Pipelined MAC is believe can speed up the operations of the previous conventional MAC plus it can reduce the time and cost. The effectiveness of pipelining concept in the system's implementation is undeniable as the performance of the system is improved where the multiplication process is pipelined with the addition process. Pipelining reduces cycle time but does not reduce the total time required for multiplication. One way to speed up multiplication is Booth Algorithm, which perform several steps of the multiplication at once. Booth's algorithm takes advantage of the fact that an adder-subtractor is nearly as fast and small as a simple adder. The implementation of Accumulator using Carry Look-ahead Adder (CLA) technique has brought to fast operation achieved in addition process of 8-bit data. The pipeline MAC is designed to increase the speed of MAC operations, decrease the cycle time and to avoid the delay in the conventional MAC.

    Item Type: Thesis ( Undergraduates)
    Additional Information: Academic Exercise (Bachelor’s Degree) – Faculty of Computer Science & Information Technology, University of Malaya, 2002/2003.
    Uncontrolled Keywords: Pipelined Multiplier Accumulator; Pipelined MAC; Booth Algorithm
    Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
    Q Science > QA Mathematics > QA76 Computer software
    Divisions: Faculty of Computer Science & Information Technology
    Depositing User: Mr Mahadie Ab Latif
    Date Deposited: 30 Jun 2021 11:07
    Last Modified: 30 Jun 2021 11:07
    URI: http://studentsrepo.um.edu.my/id/eprint/10169

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