Marina , Haryati Mohammad (2005) Smart transducer interface module (main state machine VHDL) / Marina Haryati Mohammad. Undergraduates thesis, University of Malaya.
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Abstract
This project is about the development of Smart Transducer Interface Module in hardware. The IEEE1451.2 smart sensor approach specifies a 'plug and play' capability in a transducer module, which is achieved through transducer electronic data sheet (TEDS). It specifies a digital interface to access TEDS and transducer are defined. This STIM will be implemented using VHSIC Hardware Description Language (VHDL). Peak FPGA software. This report will comprise the ST1M phase from the design phase of main state machine until the end of testing phase.
| Item Type: | Thesis ( Undergraduates) |
|---|---|
| Additional Information: | Academic Exercise (Bachelor’s Degree) - Faculty of Computer Science & Information Technology, 2004/2005. |
| Uncontrolled Keywords: | Smart Transducer Interface Module; Transducer electronic data sheet (TEDS); Hardware Description Language (VHDL) |
| Subjects: | Q Science > QA Mathematics > QA75 Electronic computers. Computer science Q Science > QA Mathematics > QA76 Computer software |
| Divisions: | Faculty of Computer Science & Information Technology |
| Depositing User: | Mr Mohd Zaimi Izwan Kamarunsaman |
| Date Deposited: | 27 Jul 2021 07:12 |
| Last Modified: | 27 Jul 2021 07:12 |
| URI: | http://studentsrepo.um.edu.my/id/eprint/11580 |
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