Design of low power front-end receiver for bluetooth low energy/ZigBee in nano-scale CMOS technology / Zechariah Balan

Zechariah, Balan (2019) Design of low power front-end receiver for bluetooth low energy/ZigBee in nano-scale CMOS technology / Zechariah Balan. Masters thesis, University Malaya.

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      With the increasing need for the internet of things (IoT), Bluetooth low energy (BLE) and ZigBee standards have become popular solutions for wireless devices. In the tremendous growth of wireless application, low voltage and low power consumption have become a major consideration in radio frequency integrated circuit (RFIC). The development of low power transceiver is driven by the need of withstanding longer battery life time and reduced cost, catering towards mobile application. The continuous downscaling of deep-submicron CMOS technologies to reduce overall power consumption and enable high frequency operation outlays design challenges in the construction of RF front end blocks, which results in less voltage headroom available for circuits to operate. This has driven the need in exploration of new low power/low voltage design technique for RF architecture. The performance of a receiver is dependent on that of the individual blocks such as low noise amplifier (LNA), mixer and voltage controlled oscillator (VCO). This dissertation focuses on the design and implementation of a 1.5V ultra-low power 2.4-GHz CMOS receiver powered by a coin battery. The proposed receiver is relaxed in the use of a low dropout regulator (LDO). By effective merging of the quadrature low noise amplifier (QLNA), in phase and quadrature (I/Q) mixers, VCO and trans-impedance amplifier (TIA) in one cell, while removing the LDO, the available 1.5-V voltage supply is fully utilized for current reuse between blocks, minimizing the dc current consumption. Specifically, a quadrature LNA operating as both common-source and common drain topologies provides the I/Q outputs in the RF signal path. The forward body bias technique is applied to the transconductance stage of the I/Q mixers to relax its voltage headroom consumption. Implemented in 180-nm CMOS technology, the receiver exhibits a conversion gain (CG) of 24 dB, a noise figure (NF) of 13.8 dB and an input-referred iv 3rd-order intercept point (IIP3) of -14 dBm while consuming only 2 mA. The phase noise of the VCO is -118.5 dBc/Hz at 2.5 MHz offset. The low-cost technology and low current consumption renders the receiver suitable for Internet of Things (IoT) devices using the Bluetooth Low Energy (BLE) or ZigBee standards.

      Item Type: Thesis (Masters)
      Additional Information: Dissertation (M.A.) - Faculty of Engineering, University of Malaya, 2019.
      Uncontrolled Keywords: IQ Receiver; Low power; ZigBee; Bluetooth low energy (BLE); CMOS technology
      Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
      Divisions: Faculty of Engineering
      Depositing User: Mrs Rafidah Abu Othman
      Date Deposited: 06 Apr 2021 01:33
      Last Modified: 06 Apr 2021 01:33

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