Design and fabrication of low power differential low noise amplifier for WLAN application in deep sub-micron standard CMOS technology / Maizan Muhamad

Maizan, Muhamad (2019) Design and fabrication of low power differential low noise amplifier for WLAN application in deep sub-micron standard CMOS technology / Maizan Muhamad. PhD thesis, Universiti Malaya.

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      This thesis presents the design and implementation of low power differential low noise amplifier for wireless local area network application. The operating frequency was designed at 2.4 GHz with a supply headroom of 1.2 V and implemented on Silterra’s 0.13μm RF CMOS process. A detailed methodology that leads to a power efficient design of the circuit is presented. Then, a comprehensive circuit analysis and design methodology of the differential cascode topology, that is the differential Power-Constrained Simultaneous Noise and Input Matching low noise amplifier. A theoretical noise figure optimization using fixed power and physics-based characteristics were used as a design optimization guide. Simultaneous noise and input matching under constrained power was achieved with an extra gate source capacitor while gain enhancement was obtained by employing a capacitive feedback at the cascode transistor. Scattering parameter measurement of differential four-port networks low noise amplifier requires a four-port vector network analyzer. Thus, a measurement technique that enables very accurate measurement for S-parameter of differential low noise amplifier by means of a standard two-port vector network analyzer is presented. This technique involves by terminating two ports at one time while another two ports are measured. Apart from that, a general noise figure de-embedding technique also presented in this thesis. De-embedding noise figure measurement of a differential low-noise amplifier based on the analysis of two gain definitions. The effects of impedance match on noise figure are investigated. The result shows a noise figure of 0.57 dB obtained with the de-embedding technique and 1.2 dB without the de-embedding technique. Noise figure was measured under three different source impedances namely short, open and load. The end-design of the optimized differential low noise amplifier produces a power gain of 17.12dB with a dc power consumption of 7.2mW. A linearity of -10.5 dBm achieved. The LNA has been experimentally verified for its functionality and results a validated peak the performance at 2.4 GHz of operating frequency

      Item Type: Thesis (PhD)
      Additional Information: Thesis (PhD) - Faculty of Engineering, Universiti Malaya, 2019.
      Uncontrolled Keywords: Amplifier; WLAN application; De-embedding technique; Cascode transistor; GHz
      Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
      Divisions: Faculty of Engineering
      Depositing User: Mr Mohd Safri Tahir
      Date Deposited: 16 Mar 2022 07:36
      Last Modified: 16 Mar 2022 07:36

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