Design of ultra low voltage, high efficiency CMOS radio frequency energy harvesting system / Yong Jack Kee

Yong , Jack Kee (2024) Design of ultra low voltage, high efficiency CMOS radio frequency energy harvesting system / Yong Jack Kee. PhD thesis, Universiti Malaya.

	PDF (The Candidate's Agreement) Restricted to Repository staff only Download (143Kb)
	PDF (Thesis PhD) Download (2540Kb)

Abstract

Wireless Sensor Networks (WSNs) have emerged as a pivotal technology for various IoT applications, driven by advancements in 5G (5th Generation) technology and cloud computing. For stable and continuous operation, Radio Frequency Energy Harvesting (RFEH) is considered an optimal energy source for WSNs to achieve self-power capabilities, alleviating the need for a battery. The rectifier and charge pump (CP) plays a crucial role within the Radio Frequency Energy Harvesting (RFEH) system. However, the performance is significantly impacted by high conduction and reversion loss in subthreshold operation. Despite the existence of dynamic gate biasing (DGB) techniques that aim to mitigate both conduction and reversion losses, these losses cannot be entirely eliminated, resulting in the low performance of the rectifier and CP circuit. Furthermore, the broad range of scavenged input power from the RFEH system can result in elevated output voltage levels that may pose a risk of damaging the WSN load. This thesis presents a comprehensive review of recent rectifier and CP improvement techniques and provides a thorough analysis of the characteristics of the state-of-the-art rectifier and CP circuit. By considering the trade-offs, several enhancements are proposed to optimize these components specifically for subthreshold operation, aiming to improve its power conversion efficiency (PCE). This work proposes a novel advance dynamic gate-biasing technique that focuses on reducing forward conduction loss and reverse current leakage loss in the rectifier and CP. Specifically, the advanced DGB is combined with an NMOS-PMOS dual-switch transistor pair which acts as a secondary switch to further reduce the losses. By implementing this combination, the proposed architecture achieved an ultra-low-voltage input (0.1 V) subthreshold operation CP with a PCE of 43.4 %. Additionally, a novel reconfigurable series-parallel CP employing a dynamic source-fed oscillator with 62 % PCE is introduced. Finally, an integrated RFEH featuring a low-power voltage monitoring unit with 3.3 V bounded output cater is designed to cater to WSN applications. The research contributes to the understanding and advancement of rectifiers and CPs, and the design of a fully integrated RFEH system, enabling more efficient energy utilization in WSNs.

Actions (For repository staff only : Login required)