DC-link voltage balancing and common-mode current reduction of five-level diode-clamped inverter / Rosmadi Abdullah

Rosmadi , Abdullah (2019) DC-link voltage balancing and common-mode current reduction of five-level diode-clamped inverter / Rosmadi Abdullah. PhD thesis, University of Malaya.

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Abstract

Multilevel inverters have gained much attention in the application of medium voltage and high power, owing to their various advantages such as lower voltage stress on power switches and lower dv/dt ratio which supply lower harmonic contents in output voltage and current. Instead of its merits for high-voltage applications, a five-level diode-clamped inverter is prone to unbalance of the dc-link voltage capacitor at the inverter input. The voltage unbalance phenomenon deteriorates the inverter output voltage waveforms and consequently, results in unsatisfactory performance or even failure of the diode-clamped inverter. This thesis proposes an active front-end solution to balance dc-link capacitor voltage of five-level diode-clamped inverter. Capacitor voltage balancing performed by three-level boost converter connected to the two inner capacitors of five-level diode-clamped inverter have additional balancing circuits at other two outer capacitors. Another problem with five-level diode-camped is common-mode current to the ground through parasitic capacitor which is between the photovoltaic array and the ground in grid-connected photovoltaic system. In addition to safety issue, high common-mode current can cause distortion in the grid current waveform, serious electromagnetic interferences, and increased losses in the photovoltaic system. The amplitude of the leakage current is dependent on the converter topology and pulse width modulation technique used. This study also proposes a switching modulation technique using modified space-vector and pulse-width modulation for leakage current reduction in a transformerless five-level diode-clamped inverter. Selective vectors are used in the modulation technique to produce an invariable common-mode voltage that leads to the reduction of the common-mode current. The effect of dead-time on the magnitude of the leakage current was also investigated. The validity of the proposed configuration for dc-link capacitor voltage balancing and common-mode leakage current reduction is verified via simulations work using Matlab/ Simulink and laboratory prototypes. DSP TMS320F28335 is used to generate a modified space-vector modulation technique to eliminate common-mode and leakage current reduction. It is also used to control the duty cycle of the balancing circuit. Proposed configuration is tested through simulation and experiment for various load power factor conditions at high modulation index. The result demonstrates the reliability of proposed configuration to balance the dc-link capacitors voltage at desired level. The performances of the proposed modulation technique in terms of common-mode voltage, leakage current and total harmonic distortion (THD) are compared with conventional sinusoidal pulse-width modulation technique. The simulation and experimental work is validated.

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