Development of techniques for in-situ monitoring stress-induced degradation and potential solutions for FPGA / Anuar Jaafar

Anuar , Jaafar (2022) Development of techniques for in-situ monitoring stress-induced degradation and potential solutions for FPGA / Anuar Jaafar. PhD thesis, Universiti Malaya.

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Abstract

Reliability and application failures occurring in Field Programmable Gate Arrays (FPGAs) are pressing issues in today’s specific FPGA application. This is due to the high density of logic circuits on the chip subsequent to rapid process technology scaling. Reliability issues in FPGA lead to the degradation in the FPGA performance, leading to a shorter device lifetime. Negative Bias Temperature Instability (NBTI) degradation effect occurs due to the chemical breakdown between gate-dielectric-channel regions of a Positive Metal-Oxide-Semiconductor (PMOS) transistor. The logic delay occurrence on FPGA is mainly caused by the NBTI effect that substantially reduces the FPGA's lifespan. A ring oscillator has been widely used as a digital temperature sensor to sense logic delay degradation subsequent to the thermal effect on FPGAs. The logic delay generated by the ring oscillator is caused by temperature changes that lead to the electromigration degradation effect. The decreasing of electron mobility causes the propagation delay to decrease as well. Therefore, it is critical to adopt an accurate ring oscillator design to effectively measure the logic delay in FPGAs. This work proposes to develop automatic clock correction tools to rectify degradation occurrence due to logic delay effect in order to sustain the FPGA performance. This work also proposes to design a stable ring oscillator to detect the logic delay degradation due to thermal effect during optimum temperature operation. Furthermore, a lifetime prediction table as a guideline for the system designer or industrial operators is also proposed, in which it provides an indication of a critical level of when the FPGA is prone to fail. Measurement periods of 512 and 4096 clock cycles have been implemented and the relationship between temperature, logic delay and total count has been developed. Logic delay is converted to phase degree using a special function that considers the relationship between time and frequency. The logic delay that is triggered by an FPGA can be in multiple ranges of phase from 0˚ to 360˚. All possible ranges of delays, each corresponding to a particular amount of degradation, have been investigated by implementing an exhaustive test in estimating the lifetime of a device. It is observed that when the logic delay increases by 50˚, the lifetime will decrease by 13.89%. Through the critical level obtained from the technique proposed, a user can indicate the schedule of a replacement FPGA unit for continual process in maintaining the reliability of the FPGA. It has been found that the best measurement period to reduce the degradation effect on the Virtex-6 FPGA is to adopt a measurement period of 512 clock cycles on various temperature-based FPGAs ranging from 0℃ until 100℃. In summary, the effect of NBTI on FPGA has been demonstrated based on the logic delay degradation via aging detection and high operating temperature of the FPGA. Finally, the developed lifetime prediction table helps to indicate system designers and industrial operators of when to replace the FPGA in their electronic systems in order to prolong the performance of the FPGA.

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