Device characterization based on stressor, geometric and process design considerations of fet technology / Nurul Aida Farhana Othman

Nurul Aida Farhana, Othman (2018) Device characterization based on stressor, geometric and process design considerations of fet technology / Nurul Aida Farhana Othman. Masters thesis, University of Malaya.

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Abstract

The downscaling of complementary metal-oxide-semiconductor (CMOS) device has been tremendously feasible in the past couple of decades. This action has led to a constant escalation of devices count in a dense integrated circuit, hence an outstanding application of Moore’s law to the industry especially in semiconductor sector. Nevertheless, the reduction in the sizing of features has bound to become an issue in providing excellent performance in CMOS circuits particularly in drive current maintenance and operating speed efficiency. Therefore, designers have proposed several solutions to replace the conventional metal-oxide-semiconductor field effect transistor (MOSFET) designs such as the implementation of strain/stress engineering technology, introduction of multi-gated MOSFET, adoption of group IV and III-V semiconductors into the device structure, and scaling specification validated with statistical techniques and numerical methods. This work presents a comprehensive simulation study and optimization analysis to study the impacts of stressor, geometric and process design considerations on novel FET devices, i.e. fin shaped FET (FinFET) and heterostructure FET (HFET), for low and high power applications, respectively. A technology computer-aided design (TCAD) based tools, i.e. Synopsys Sentaurus TCAD is used to demonstrate the design structures and analysis on the investigated FET devices. The impact of specific parameters selection on the device performance are considered based on standard CMOS manufacturing trends in recent years. The implementation of germanium (Ge) and aluminium nitride (AlN) in 7 nm FinFET and gallium nitride (GaN) based HFET, respectively, as the stressor effects has allowed the adjustment of threshold voltage roll-off behaviour without dramatically degrading the device drive current. The incorporation of stress inside the channel layer can increase the drain current by ~110% and ~57% for p- and n-FinFET, respectively. For GaN based HFET, insertion of AlN as the interfacial layer with high Al mole fraction in the barrier can increase the current up to 48% and improve the mobility as well as carrier confinement. Besides that, device performances were explored through varied geometric and process design parameters of a certain range of values. The devices were electrically characterized by studying the current-voltage relation and several figure-of-merits were extracted to study the impacts of these design consideration. This work shows that both geometric and process considerations are affecting the FET performances with similar importance. An optimization process is also conducted onto the 7 nm Ge based FinFET by optimizing the fin geometry. Taguchi method and Pareto analysis of variance were implemented in order to achieve the best possible design for each specification and response with respect to threshold voltages, drive currents, and subthreshold leakages. The analysis shows that the device geometry designs are highly affecting device performances especially the gate length, top fin width, and the interaction of both for n- and p-FinFET by more than 50%. Since the geometries are related to each other in performance improvements, it is important to choose the most nominal design for threshold and current trade-offs achievements. In conclusion, this work has characterized the impact of group IV and III-V stressor on the FET devices and considering the geometrical and process design, producing simulation results which were in qualitative agreement with published results by other researchers. It is important to understand and simulate accurately the effects of specific parameter selections in the initial design phase to guarantee the optimal operation and limitation of devices in order to realize acceptable CMOS performance for particular chip specifications.

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