Studies on flat CORDIC implementation in field programmable gate arrays (FPGA) / Meera Subramaniam

Meera , Subramaniam (2004) Studies on flat CORDIC implementation in field programmable gate arrays (FPGA) / Meera Subramaniam. Masters thesis, Universiti Malaya.

PDF (Thesis M.A.) Download (671Kb)

Abstract

The CORDIC algorithm has been widely researched as an efficient hardware algorithm for the computation of trigonometric, hyperbolic and transcendental functions. It is an iterative process of rotations that are carried out through simple shift and addition operations. These operations map well onto hardware, and CORDIC is used in a multitude of signal processing applications. The iterative nature of CORDIC is a drawback, and a technique known as Flat CORDIC was introduced to eliminate the iterations, making the design largely combinatorial. The latest advances in VLSI technology have made it possible to produce series of FPGAs that have large numbers of gates at relatively low costs. This work focuses on FPGA implementation of the Flat CORDIC scheme to efficiently compute trigonometric functions. The successive replacement of the basic CORDIC equations to generate the parallelized Flat CORDIC ones requires that the direction of all the rotations be pre-computed. This work presents a modification to the previous Signed Digit (SD) Generation algorithm and a comparison with the previous method. The second major component is the mapping of the Flat CORDIC equations using these SDs. An architecture is proposed for effective combination of these SDs for sine/cosine generation. Pipelining methods are investigated to increase design speed. The architectures for 9, 12, 15, 18, 21 and 24 bit Flat CORDIC are simulated using XILINX ISE WebPack 5.2i. The functionally simulated designs are synthesized onto SPARTAN FPGAs. Some relevant comparisons are made with other designs in literature. It is found that if properly pipelined, Flat CORDIC on FPGAs can achieve high speeds of up to 43 MHz for 20 bit accuracy. In terms of area, however, the largely combinatorial design is a drawback for FPGA implementation. In summary, the main contribution of this thesis is a study on the effectiveness of mapping Flat CORDIC onto FPGAs.

Actions (For repository staff only : Login required)