A VHDL implementation of BIST technique in UART design / by Mohd. Yamani Idna bin Idris.

Idris, Mohd. Yamani Idna (2002) A VHDL implementation of BIST technique in UART design / by Mohd. Yamani Idna bin Idris. Masters thesis, University of Malaya..

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                        Item Type: Thesis (Masters)
                        Additional Information: Dissertation (M.Comp.Sc.) -- Fakulti Sains Komputer dan Teknologi Maklumat, Universiti Malaya, 2003.
                        Uncontrolled Keywords: VHDL (Computer hardware description language).; Integrated circuits--Design and construction.
                        Subjects: Q Science > QA Mathematics
                        Divisions: Faculty of Computer Science & Information Technology
                        Depositing User: Puan Norashikin Ismail
                        Date Deposited: 14 Apr 2012 15:45
                        Last Modified: 23 Jul 2013 11:39
                        URI: http://studentsrepo.um.edu.my/id/eprint/2150

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